1. Field of Invention
The present invention pertains to the field of memory sense amplifiers. More particularly, this invention relates to high-density memory sense amplifiers having a controlled sense voltage and a plurality of resistive elements providing a reference current.
2. Background
In a random access memory (RAM) array, an amplifier is used to sense the state of an addressed memory cell and provide a signal representing the sensed state to the output of the array. This sense amplifier takes different forms, depending on the type of RAM array. In a static random access memory (SRAM) array or dynamic random access memory (DRAM) array, the memory is often volatile, that is, not retaining the data when the array is powered off. Such memories are often complex and require complex sensing circuitry such as steering (decoder) circuits and clocked, current mode amplifiers.
In contrast, a non-volatile memory array, such as a cross-point array, utilizes very simple compact memory cells, such as the cross-point type, concerned with long-term retention, high density and fast access. A non-volatile array may be a write-once type having a fuse or anti-fuse at each cross-point cell, or a multiple read-write variety, such as a magnetic random access memory (MRAM) array having cross-point magnetic cells each capable of changing between two or more states.
A major problem in such high-density resistive memory arrays is the need to isolate a selected memory cell from the unselected cells to obtain accurate sensing of the cell state. The closeness and miniature size of the cells causes a significant problem with xe2x80x9cparasiticxe2x80x9d leakage current from unselected cells that interfere with the current from the selected cell. Moreover, the small sizes of the cells and the conductors result in smaller voltages and currents, resulting in the need for greater preciseness in measuring the currents and voltages to accurately determine the data in the cell.
For example, in MRAM arrays, typically the magnetic state of a selected cell, and therefore the data stored by the cell, is determined by a small difference in current through the selected cell at a row and column junction in the different cell states. Sensing the resistive state of a single memory cell can be unreliable because all memory cell junctions are coupled together through many parallel paths. The resistance sensed for any given memory cell equals the resistance of the sensed memory cell junction in parallel with resistances of the cells at junctions of the other rows and columns. Moreover, small differences inherent in sense amplifiers can lead to small differential voltages applied to a resistive cross point array when attempting to sense a selected memory cell. These small differential voltages can cause parasitic or xe2x80x9csneak pathxe2x80x9d currents that interfere with the sensing of the cell states. Thus, there is a need to isolate each selected cell from the unselected cells to obtain a true read of the cell data.
U.S. Pat. No. 6,256,247 B1 granted to Pemer on Jul. 3, 2001 discloses a read circuit for high-density memory arrays that includes a differential amplifier and two direct injection preamplifiers. The preamplifiers provide xe2x80x9cequi-potentialxe2x80x9d isolation for the unselected cells by applying an equal voltage across input and output nodes of the cells, thus minimizing undesirable currents through unselected cells.
Another problem with high-density resistive memory arrays, such as arrays using MRAM cells, arises because the cell states are not measured by conductance or non-conductance, as in an anti-fuse memory. Rather the MRAM cell state is determined by minute differences in the conductivity of the cell junction causes by the change in resistance with different magnetic states. Thus, it is crucial to provide an accurate xe2x80x9cmirrorxe2x80x9d of the sensed current from the cell to the sense amplifier, as well as to provide a means of measuring the sensed current against a reliable standard to determine the state of the cell.
One approach has been to use a reference memory array in which the memory circuit stores a single bit of information in one memory cell. The data is stored in the memory cell in one state and is compared to a reference cell in a known state. The cell information is read by detecting the difference in resistance between the memory cell and the reference cell. The sense scheme in this approach relies on including a series transistor with each memory cell and reference cell for isolation necessary for reliable sensing of data in the selected memory cells. An obvious disadvantage is that the effective area of a memory array is increased because of the need for series transistors in each reference cell and memory cell An example of this reference memory approach is shown in U.S. Pat. No. 6,055,178 granted to Naji on Apr. 25, 2000.
Another approach has been to use a pair of cells to store one bit of data. The data is stored in the memory cell in one state and in the other memory cell in the opposite state. The cell information is read by detecting the difference in resistance between the memory junctions of the pair of cells, called the xe2x80x9cbit, bit barxe2x80x9d approach. The output from the cell pairs doubles the signal available for sensing, thus minimizing error. An obvious disadvantage is that the effective capacity of a memory array is cut in half because of the need for two memory cells for each stored bit. An example of this reference memory approach is shown in U.S. Pat. No. 6,191,989 granted to Luk on Feb. 20, 2001.
Accordingly, a practical circuit is needed for high-density resistive memory arrays to minimize the leakage currents from the unselected cells, such as by minimizing the voltage potential across the junctions of unselected cells. Moreover, there is a need to isolate the selected cell from the unselected cells so that any parasitic currents from unselected cells will not distort the accuracy of the selected cell current. In addition, it is important that slight differences inherent in different sense amplifiers be minimized to avoid distortions of the measured currents. Further, an accurate translation or mirroring of the sensed cell current must be provided to the sense amplifier in order to accurately measure the sensed current against a reference. Finally, an effective means of providing a reference current is needed which will not compromise the effective storage density of the array.
The present invention provides a practical circuit to integrate with a high-density memory. The circuitry of the present invention applies an accurate sense voltage to a selected cell and simultaneously to selected reference cells. It provides circuitry to apply xe2x80x9cequi-potentialxe2x80x9d isolation to minimize the parasitic effects of leakage current from unselected memory cells. It provides a means to isolate the selected cell from the unselected cells. Further, the present invention provides an accurate reference for the sensed current without requiring an entire reference memory array. Moreover, the present invention provides access and sensing of resistive memory cells while maintaining read access times comparable to other high density sensing approaches.
In one preferred embodiment of the present invention, a sense amplifier is provided for reading data in a multiple-state memory cell of a resistive memory array in response to a read voltage applied across the sensed memory cell, including a differential amplifier having first and second input nodes. A sense circuit is provided for determining the current in the memory cell with the read voltage applied thereto and applying a sense current representative of the memory cell current to the first input node of the differential amplifier. A reference circuit is provided having first and second resistive elements for applying a reference current to the second input node of the differential amplifier, the reference current providing a value against which to compare the sense current to determine the state of the memory cell.
The first resistive element has a first resistance representative of a first state of the memory cell, and the second resistive element has a second resistance representative of a second state of the memory cell. A voltage source for applying the read voltage across the first and second resistive elements to generate a reference current by averaging the currents through the first and second resistive elements. A first translator transistor applies the memory cell sense current to the first node of the differential amplifier, and a second translator transistor applies the reference current to the second node of the differential amplifier. A comparator circuit is used to compare the signals at the first and second input nodes of the differential amplifier to provide an output indicative of the state of the sensed memory cell.
Another preferred embodiment of the present invention is a method of reading data in a sensed multiple-state memory cell of a resistive memory array using a differential amplifier. The method comprises generating a current in the memory cell using a read voltage applied thereto and applying a sense current representative of the current in the memory cell current to the first input node of the differential amplifier. A reference current is generated using a reference circuit with first and second resistive elements, and the reference current is applied to the second input node of the differential amplifier, the reference current providing a value against which to compare the sense current to determine the state of the memory cell.
The reference current is generated by generating a first reference current by applying the read voltage across a first reference element having a resistance representative of a first state of the memory cell, and generating a second reference current by applying the read voltage across a second reference element having a resistance representative of a second state of the memory cell.
The first and second reference currents are averaged, and the averaged current is applied to the second input node of a differential amplifier. A supply voltage is applied across a mirror transistor to the first node of the differential amplifier to generate a sense node voltage, and across a reference transistor to the second node of the differential amplifier to generate a reference node voltage. A first voltage is generated at the first node of the differential amplifier representative of the sense current, and a second voltage is generated at the second node representative of the reference current. The first and second voltages on the first and second input nodes of the differential amplifier are compared to provide an output indicative of the state of the sensed memory cell.
Other aspects and advantages of the present invention will become apparent from the following detailed description, which in conjunction with the accompanying drawings illustrates by way of example the principles of the present invention.